Index of /hdl

	Name	Last modified	Size	Description
	Parent Directory		-
	105_20170630100630kn..>	2019-04-12 11:24	63K
	Cursoalt.zip	2014-12-05 13:15	1.3M
	Designing_with_Quart..>	2014-12-05 13:15	3.3M
	Exercicios_Q2_docs.zip	2014-12-05 13:15	491K
	SectionI.zip	2014-12-05 13:15	106K
	TOP.zip	2025-01-23 15:20	536K
	TapScanner 04-04-202..>	2022-04-04 03:52	173K
	VID_20171101_155415.3gp	2017-11-06 10:19	92M
	VID_20171101_162942.3gp	2017-11-06 10:23	76M
	VID_20171101_163502.3gp	2017-11-06 10:25	11M
	VID_20171101_164047.3gp	2017-11-06 10:29	22M
	bateux_mouches_paris..>	2024-08-06 07:25	80K
	casa.js	2021-03-23 15:50	6.4K
	casa.php	2021-03-23 15:44	281
	client.php	2022-03-12 13:08	1.5K
	components/	2021-03-20 15:02	-
	design.zip	2014-12-05 13:15	2.8M
	fpga.html	2021-06-17 15:34	3.3K
	inst.101	2021-05-14 18:24	607
	inst.s	2021-05-13 15:47	305
	ip_fun.php	2022-03-12 13:04	693
	led_counter-7.ttf	2021-03-20 15:36	250K
	lu.html	2017-11-08 10:40	50
	lu.txt	2017-11-08 10:18	21
	lupi_fpga.zip	2021-05-13 15:38	938
	mcveri.zip	2014-12-05 13:15	146M
	remote.js	2021-09-06 14:59	14K
	remote.php	2022-03-26 06:12	2.7K
	riscv1.zip	2021-07-27 14:52	7.4K
	send_sse.php	2021-09-28 10:53	864
	shift-fpga.c	2021-05-21 11:27	588
	simulate.php	2021-11-02 16:46	2.2K
	smith/	2021-02-10 07:42	-
	top.sv	2021-07-27 14:48	1.7K
	try.html	2021-03-20 15:42	201
	up_fun.php	2022-03-12 14:59	1.4K
	uploaded.php	2021-11-02 16:53	1.2K
	uploads/	2021-03-17 16:07	-
	uvm.zip	2017-02-14 14:17	32K
	vJTAG_interface.sv	2025-01-19 16:36	5.1K
	verilog-mode.el	2014-12-05 13:15	255K
	verilog.zip	2014-12-05 13:15	221K