First simulate, then upload Your Systemverilog, binary instruction code, assembly, C , or compressed file. The compressed .zip file may contain only SystemVerilog .sv files, only assembly .s files, only .c, .cpp and .h C/C++ files, a binary instruction code file called inst.101, and .jpeg., .jpg, .pdf files, or a mix of any of those. Do not use any sub-directory.
In order to get credits, You need to put Your name in the first line of the main file. You must put a comment marker at the start of that line.
In the second line, as comment, put the title of Your project.
In case You upload only one file, this is the one that needs Your name in it. Be careful to use the appropriate comment marker for the language the files is written in. In case You upload a .zip file, the main file to put Your name in is top.sv, if present. If top.sv is not present, the main file is the .c or .s file one that defines main.
main