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always @(a or b or c) e = (a|b)&(c|d);
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if (i > 0)   if (i < 2) $display ("i is 1");else $display ("i is less than 0");

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event event_1, event_2;always @ event_1 -> event_2;initial @event_2 $stop;initi
al -> event_1;
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primitive Adder(Sum, InA, InB); output Sum; input Ina, InB;table 00 : 0; 01 : 1
; 10 : 1; 11 : 0; endtable endprimitive
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primitive DLatch(Q, Clock, Data); output Q; reg Q; input Clock, Data;table 1 0
: ? : 0; 1 1 : ? : 1; 0 1 : ? : -; endtable endprimitive
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primitive DFF(Q, Clock, Data); output Q; reg Q; input Clock, Data;tabler    0 :
 ? : 0 ; r    1 : ? : 1 ; (0x) 0 : 0 : 0 ; (0x) 1 : 1 : 1 ; (?0) ? : ? : - ; ?
(??) : ? : - ;endtable endprimitive
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module JKFF (Q, J, K, Clk, Rst);parameter width = 1, reset_value = 0;input [wid
th-1:0] J, K; output [width-1:0] Q; reg [width-1:0] Q;input Clk, Rst; initial Q
 = {width{1'bx}};always @ (posedge Clk or negedge Rst )if (Rst==0 ) Q <= #1 res
et_value;else Q <= #1 (J & ~K) | (J & K & ~Q) | (~J & ~K & Q);endmodule
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module Vector_AND(Z,A,B);   parameter card = 2; input [card-1:0] A,B; output [c
ard-1:0] Z;   wire [card-1:0] Z = A & B;endmodule
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module Four_AND_Gates(OutBus, InBusA, InBusB);   input [3:0] InBusA, InBusB; ou
tput [3:0] OutBus;   Vector_AND #(4) My_AND(OutBus, InBusA, InBusB);endmodule
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module X_AND_Gates(OutBus, InBusA, InBusB);   parameter X = 2;input [X-1:0] InB
usA, InBusB;output [X-1:0] OutBus;   Vector_AND #(X) My_AND(OutBus, InBusA, InB
usB);endmodule module size; defparam X_AND_Gates.X = 4; endmodule
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nand (strong0, strong1) #1   Nand_1(n001, n004, n005),   Nand_2(n003, n001, n00
5, n002);nand (n006, n005, n002);
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nand #2 nand_array[0:7](zn, a, b);
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real ImReal; integer ImInteger;initial begin ImReal = -1.5; ImInteger = ImReal;
 end
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module nonblocking; reg Y;   always begin Y <= #10 1;Y <= #20 0;#10; end    alw
ays begin $display($time,,"Y=",Y); #10; end    initial #100 $finish;endmodule
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module Dff_Res_Bad(D,Q,Clock,Reset);output Q; input D,Clock,Reset; reg Q; wire
D;always @(posedge Clock) if (Reset!==1) Q=D; always if (Reset==1) Q=0;end endm
odule
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module DFF (D, Q, Clk, Rst);parameter width = 1,  reset_value = 0;input [width-
1:0] D; output [width-1:0] Q; reg [width-1:0] Q;input Clk,Rst;initial Q = {widt
h{1'bx}};always @ ( posedge Clk or negedge Rst )if ( Rst==0 ) Q <= #1 reset_val
ue; else Q <= #1 D;endmodule
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module DFFSCAN (D, Q, Clk, Rst, ScEn, ScIn, ScOut);parameter width = 1,  reset_
value = 0;input [width-1:0] D; output [width-1:0] Q; reg [width-1:0] Q;input Cl
k,Rst,ScEn,ScIn; output ScOut;initial Q = {width{1'bx}};always @ ( posedge Clk
or negedge Rst ) begin   if ( Rst==0 )                   Q <= #1 reset_value;
  else if (ScEn)                   Q <= #1 {Q,ScIn};   else
     Q <= #1 D;end assign ScOut=Q[width-1];endmodule
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module PadBidir (C, Pad, I, Oen); // active low enableparameter width=1, pinNum
bers="", \strength =1, level="CMOS",pull="none", externalVdd=5;output [width-1:
0] C; inout  [width-1:0] Pad; input  [width-1:0] I;input Oen;assign #1 Pad = Oe
n ? {width{1'bz}} : I;assign #1 C = Pad;endmodule
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module Loop_Bad; reg [3:0] i; reg [31:0] DBus;initial DBus = 0;initial begin #1
; for (i=0; i<=15; i=i+1) DBus[i]=1; endinitial begin$display("DBus = %b",DBus)
; #2; $display("DBus = %b",DBus); $stop;end endmodule
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integer IntA;IntA = -12 / 3; // result is -4IntA = -'d 12 / 3; // result is 143
1655761
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integer intA; reg [15:0] regA;intA = -4'd12; regA = intA/3; regA = -4'd12; intA
 = regA/3; intA = -4'd12/3; regA = -12/3;
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reg [7:0] a, b, sum; sum = (a + b) >> 1;
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sum = (a + b + 0) >> 1; sum = {0,a} + {0,b} >> 1;
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assign p = q; initial begin q = 0; #1 q = 1; $display(p); end
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module test (.a(c), .b(c));
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module e1; reg a, b, c;initial begin a = 0; b = 1; c = 0; end always c = #5 ~c;
 always @(posedge c) begin a <= b; b <= a; endendmodule
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module e2; reg a, b, c, d, e, f;initial begin a = #10 1; b = #2 0; c = #4 1; en
d initial begin d <= #10 1; e <= #2 0; f <= #4 1; end endmodule
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module e3; reg a, b;initial begin a = 0; b = 1; a <= b; b <= a; end endmodule
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module m1; reg a;initial a = 1;initial begin a <= #4 0; a <= #4 1; end endmodul
e
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module m2; reg r1; reg [2:0] i;initial begin r1 = 0; for (i = 0; i <= 5; i = i+
1) r1 <= # (i*10) i[0]; endendmodule
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module stop (); initial #1 $finish; endmodulemodule Outs_1 (a); output [3:0] a;
 reg [3:0] a;initial a <= 4'b10xz; endmodulemodule Outs_2 (a); output [2:0] a;
reg [3:0] a;initial a <= 4'b10xz; endmodulemodule Outs_3 (a); output [3:0] a; r
eg [2:0] a;initial a <= 4'b10xz; endmodulemodule Outs_4 (a); output [2:0] a; re
g [2:0] a;initial a <= 4'b10xz; endmodulemodule Outs_5 (a); output a; reg [3:0]
 a;initial a <= 4'b10xz; endmodulemodule Outs_6 (a[2:0]); output [3:0] a; reg [
3:0] a;initial a <= 4'b10xz; endmodulemodule Outs_7 (a[1]); output [3:0] a; reg
 [3:0] a;initial a <= 4'b10xz; endmodulemodule Outs_8 (a[1]); output a; reg [3:
0] a; always a <= 4'b10xz; endmodule
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module XOR_spec (a, b, z); input a, b: output z; xor x1 (z, a, b);specify   spe
cparam tnr = 1, tnf = 2 specparam tir = 3, tif = 4;   if ( a)(b => z) = (tir, t
if); if ( b)(a => z) = (tir, tif);   if (~a)(b => z) = (tnr, tnf); if (~b)(a =>
 z) = (tnr, tnf);endspecifyendmodule
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module counter (data_in, up, down, clock,    count_out, carry_out, borrow_out,
parity_out);output [8:0]  count_out;output carry_out, borrow_out, parity_out;in
put  [8:0]  data_in; input clock, up, down;reg    [8:0]  count_out; reg carry_o
ut,  borrow_out, parity_out;// insert your design here endmodule
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module dff(q, qbar, clock, data, preset, clear);
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`define M_MAX(a, b)((a) > (b) ? (a) : (b))`define M_ADD(a,b) (a+b)module macro;
reg m1, m2, m3, s0, s1;`define var_nand(delay) nand #delay `var_nand (2) g121 (
q21, n10, n11);`var_nand (3) g122 (q22, n10, n11);initial begin s0=0; s1=1;m1 =
 `M_MAX (s0, s1); m2 = `M_ADD (s0,s1); m3 = s0 > s1 ? s0 : s1;end initial #1 $d
isplay(" m1=",m1," m2=",m2," m3=",m3);endmodule
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