__________________________________________________________________________ // comp_mux.vmodule comp_mux(a, b, outp); input [2:0] a, b; output [2:0] outp;f unction [2:0] compare; input [2:0] ina, inb;begin if (ina <= inb) compare = ina ; else compare = inb; endendfunction assign outp = compare(a, b);endmodule __________________________________________________________________________ // testbench.vmodule comp_mux_testbench;integer i, j;reg [2:0] x, y, smaller; w ire [2:0] z;always @(x) $display("t x y actual calculated");initial $monitor ("%4g",$time,,x,,y,,z,,,,,,,smaller);initial $dumpvars; initial #1000 $finish; initial begin for (i = 0; i <= 7; i = i + 1) begin for (j = 0; j <= 7; j = j + 1) begin x = i; y = j; smaller = (x <= y) ? x : y; #1 if (z != smaller) $display("error"); end end end comp_mux v_1 (x, y, z);endmodule __________________________________________________________________________ `timescale 1ns / 10ps // comp_mux_o2.vmodule comp_mux_o (a, b, outp);input [2: 0] a; input [2:0] b;output [2:0] outp;supply1 VDD; supply0 VSS;mx21d1 b1_i1 (. i0(a[0]), .i1(b[0]), .s(b1_i6_zn), .z(outp[0]));oa03d1 b1_i2 (.a1(b1_i9_zn), .a 2(a[2]), .b1(a[0]), .b2(a[1]), .c(b1_i4_zn), .zn(b1_i2_zn));nd02d0 b1_i3 (.a1 (a[1]), .a2(a[0]), .zn(b1_i3_zn));nd02d0 b1_i4 (.a1(b[1]), .a2(b1_i3_zn), .zn(b 1_i4_zn));mx21d1 b1_i5 (.i0(a[1]), .i1(b[1]), .s(b1_i6_zn), .z(outp[1]));oa04d1 b1_i6 (.a1(b[2]), .a2(b1_i7_zn), .b(b1_i2_zn), .zn(b1_i6_zn));in01d0 b1_i7 ( .i(a[2]), .zn(b1_i7_zn));an02d1 b1_i8 (.a1(b[2]), .a2(a[2]), .z(outp[2]));in01d 0 b1_i9 (.i(b[2]), .zn(b1_i9_zn));endmodule __________________________________________________________________________ `timescale 1 ns / 10 psmodule mx21d1 (z, i0, i1, s); input i0, i1, s; output z; not G3(N3, s); and G4(N4, i0, N3), G5(N5, s, i1), G6(N6, i0, i1); or G7( z, N4, N5, N6);specify (i0*>z) = (0.279:0.504:0.900, 0.276:0.498:0.890); ( i1*>z) = (0.248:0.448:0.800, 0.264:0.476:0.850); (s*>z) = (0.285:0.515:0.920 , 0.298:0.538:0.960);endspecify endmodule __________________________________________________________________________ `timescale 1 ns / 10 psmodule nd02d0 (zn, a1, a2);input a1, a2; output zn;nand G2(zn, a1, a2);specify(a1*>zn)=(0.031:0.056:0.100, 0.025:0.045:0.080);(a2*>zn)= (0.046:0.084:0.150, 0.025:0.045:0.080);endspecifyendmodule`timescale 1 ns / 10 psmodule in01d0 (zn, i); input i; output zn;not G2(zn, i);specify(i*>zn)=(0.028 :0.050:0.090, 0.025:0.045:0.080);endspecifyendmodule`timescale 1 ns / 10 psmodu le oa03d1 (zn, a1, a2, b1, b2, c); input a1, a2, b1, b2, c; output zn;or G2(N2, a1, a2), G3(N3, b1, b2); not G4(zn, N5); and G5(N5, N2, N3, c);specify(a1*>zn) =(0.381:0.689:1.230, 0.338:0.610:1.090);(a2*>zn)=(0.391:0.706:1.260, 0.360:0.65 0:1.160);(b1*>zn)=(0.338:0.610:1.090, 0.329:0.594:1.060);(b2*>zn)=(0.347:0.627: 1.120, 0.369:0.666:1.190);(c*>zn)=(0.298:0.538:0.960, 0.381:0.689:1.230);endspe cifyendmodule`timescale 1 ns / 10 psmodule an02d1 (z, a1, a2); input a1, a2; ou tput z;and G2(z, a1, a2);specify(a1*>z)=(0.118:0.213:0.380, 0.143:0.258:0.460); (a2*>z)=(0.118:0.213:0.380, 0.161:0.291:0.520);endspecifyendmodulemodule oa04d1 (zn, a1, a2, b); input a1, a2, b; output zn;or G2(N2, a1, a2); nand G3(zn, N2, b);specify(a1*>zn)=(0.288:0.521:0.930, 0.270:0.487:0.870);(a2*>zn)=(0.301:0.54 3:0.970, 0.304:0.549:0.980);(b*>zn)=(0.217:0.392:0.700, 0.291:0.526:0.940);ends pecifyendmodule __________________________________________________________________________ `timescale 1 ps / 1 ps // comp_mux_testbench2.vmodule comp_mux_testbench2;inte ger i, j; integer error;reg [2:0] x, y, smaller; wire [2:0] z, ref;always @(x) $display("t x y derived reference");// initial $monitor("%8.2f",$time/1e 3,,x,,y,,z,,,,,,,,ref);initial $dumpvars; initial begin error = 0; #1e6 $dis play("%4g", error, " errors"); $finish; end initial begin for (i = 0; i < = 7; i = i + 1) begin for (j = 0; j <= 7; j = j + 1) begin x = i; y = j; #10e3; $display("%8.2f",$time/1e3,,x,,y,,z,,,,,,,,ref); if (z != ref) begin $display("error"); error = error + 1; end end end end comp_mux_o v_1 (x, y, z); // comp_mux_o2.vreference v_2 (x, y, ref);endmodu le // reference.vmodule reference(a, b, outp);input [2:0] a, b;output [2:0] out p; assign outp = (a <= b) ? a : b; // different from comp_muxendmodule __________________________________________________________________________ function "and"(l,r : std_ulogic_vector) return std_ulogic_vector is alias lv : std_ulogic_vector (1 to l'LENGTH ) is l; alias rv : std_ulogic_vector (1 to r'LENGTH ) is r;variable result : std_ulogic_vector (1 to l'LENGTH );constant and_table : stdlogic_table := ( ----------------------------------------------- --------------| U X 0 1 Z W L H - | |-------- --------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', 'U', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) , -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', ' X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', ' X', '0', 'X', 'X' ), -- | - |);begin if (l'LENGTH /= r'LENGTH) then assert f alse report "arguments of overloaded 'and' operator are not of the samelength" severity failure; else for i in result'RANGE loop result(i) := and_table ( lv(i), rv(i) ); end loop; end if; return result;end "a nd"; __________________________________________________________________________ `celldefine `delay_mode_path `suppress_faults `enable_portfaults `timescale 1 n s / 1 ps module in01d1 (zn, i); input i; output zn; not G2(zn, i);specify specp aram InCap$i = 0.060, OutCap$zn = 0.038, MaxLoad$zn = 1.538,R_Ramp$i$zn = 0.542 :0.980:1.750, F_Ramp$i$zn = 0.605:1.092:1.950;specparam cell_count = 1.000000; specparam Transistors = 4 ;specparam Power = 1.400000; specparam MaxLoadedRamp = 3 ; (i => zn) = (0.031:0.056:0.100, 0.028:0.050:0.090); endspecify endmodul e `nosuppress_faults`disable_portfaults`endcelldefine __________________________________________________________________________ `timescale 1 ns / 1 psmodule SDF_b; reg A; in01d1 i1 (B, A);initial begin A = 0 ; #5; A = 1; #5; A = 0; endinitial $monitor("T=%6g",$realtime," A=",A," B=",B); endmodule __________________________________________________________________________ (DELAYFILE (SDFVERSION "3.0") (DESIGN "SDF.v") (DATE "Aug-13-96") (VENDOR " MJSS") (PROGRAM "MJSS") (VERSION "v0") (DIVIDER .) (TIMESCALE 1 ns) (CELL (CELLTYPE "in01d1") (INSTANCE SDF_b.i1) (DELAY (ABSOLUTE (IOP ATH i zn (1.151:1.151:1.151) (1.363:1.363:1.363)) )) )) __________________________________________________________________________ `timescale 1 ns / 1 psmodule SDF_b; reg A; in01d1 i1 (B, A);initial begin $sdf_ annotate ( "SDF_b.sdf", SDF_b, , "sdf_b.log", "minimum", , );A = 0; #5; A = 1; #5; A = 0; endinitial $monitor("T=%6g",$realtime," A=",A," B=",B);endmodule __________________________________________________________________________ -- backannotation Macro INVERTERlibrary IEEE; use IEEE.STD_LOGIC_1164.all;libra ry COMPASS_LIB; use COMPASS_LIB.COMPASS_ETC.all;entity bknot is generic (der ating : REAL := 1.0; Z1_cap : REAL := 0.000; INSTANCE_NAME : STRING := "bk not"); port (Z2 : in Std_Logic; Z1 : out STD_LOGIC);end bknot;architecture bk not of bknot isconstant tplh_Z2_Z1 : TIME := (1.00 ns + (0.01 ns * Z1_Cap)) * d erating;constant tphl_Z2_Z1 : TIME := (1.00 ns + (0.01 ns * Z1_Cap)) * derating ;begin process(Z2) variable int_Z1 : Std_Logic := 'U'; variable tplh_Z1, tphl_Z1, Z1_delay : time := 0 ns; variable CHANGED : BOOLEAN; begin int _Z1 := not (Z2); if Z2'EVENT then tplh_Z1 := tplh_Z2_Z1; tphl_Z1 := tph l_Z2_Z1; end if; Z1_delay := F_Delay(int_Z1, tplh_Z1, tphl_Z1); Z1 <= int _Z1 after Z1_delay; end process;end bknot;configuration bknot_CON of bknot is for bknot end for;end bknot_CON; __________________________________________________________________________ library IEEE; use IEEE.STD_LOGIC_1164.all;use IEEE.VITAL_timing.all; use IEEE.V ITAL_primitives.all;entity IN01D1 is generic ( tipd_I : VitalDelayType01 := (0 ns, 0 ns); tpd_I_ZN : VitalDelay Type01 := (0 ns, 0 ns) ); port ( I : in STD_LOGIC := 'U'; ZN : out STD_LOGIC := 'U' );attribute VITAL_ LEVEL0 of IN01D1 : entity is TRUE;end IN01D1;architecture IN01D1 of IN01D1 i s attribute VITAL_LEVEL1 of IN01D1 : architecture is TRUE;signal I_ipd : STD_LOGIC := 'X';begin WIREDELAY:block begin VitalWireDelay(I_ ipd, I, tipd_I); end block;VITALbehavior:process (I_ipd)variable ZN_zd : STD_LOGIC;variable ZN_GlitchData : VitalGlitchDataType; begin ZN_zd := VitalINV(I_ipd);VitalPathDelay01( OutSignal => ZN, OutSignalName => "ZN", OutTemp => Z N_zd, Paths => (0 => (I_ipd'LAST_EVENT, tpd_I_ZN, TRUE)) , GlitchData => ZN_GlitchData, DefaultDelay => VitalZeroDelay01, Mode => OnEvent, MsgOn => FALSE, XOn => TRUE, MsgSeverity => ERROR); end process;end IN01D1; __________________________________________________________________________ library IEEE; use IEEE.STD_LOGIC_1164.all;entity SDF is port ( A : in STD_LOGIC ; B : out STD_LOGIC );end SDF;architecture SDF of SDF iscomponent in01d1 port ( I : in STD_LOGIC; ZN : out STD_LOGIC ); end component; begin i1: in01d1 port map ( I => A, ZN => B);end SDF;library STD; use STD.TEXTIO.all;library IEEE; u se IEEE.STD_LOGIC_1164.all;entity SDF_testbench is end SDF_testbench;architectu re SDF_testbench of SDF_testbench iscomponent SDF port ( A : in STD_LOGIC; B : out STD_LOGIC );end component;signal A, B : STD_LOGIC := '0';begin SDF_b : S DF port map ( A => A, B => B); process begin A <= '0'; wait for 5 ns; A <= '1'; wait for 5 ns; A <= '0'; wait; end process; process (A, B) variable L: LINE; begin write(L, now, right, 10, TIME'(ps)); write( L, STRING'(" A=")); write(L, TO_BIT(A)); write(L, STRING'(" B=")); write( L, TO_BIT(B)); writeline(output, L); end process;end SDF_testbench; __________________________________________________________________________ (DELAYFILE (SDFVERSION "3.0") (DESIGN "SDF.vhd") (DATE "Aug-13-96") (VENDOR "MJSS") (PROGRAM "MJSS") (VERSION "v0") (DIVIDER .) (TIMESCALE 1 ns) (CEL L (CELLTYPE "in01d1") (INSTANCE i1) (DELAY (ABSOLUTE (IOPATH i zn (1.151:1.151:1.151) (1.363:1.363:1.363)) (PORT i (0.021:0.021:0.02 1) (0.025:0.025:0.025)) )) )) __________________________________________________________________________ (DELAYFILE (SDFVERSION "1.0") (DESIGN "halfgate_ASIC_u") (DATE "Aug-13-96 ") (VENDOR "Compass") (PROGRAM "HDL Asst") (VERSION "v9r1.2") (DIVIDER .) (TIMESCALE 1 ns) (CELL (CELLTYPE "in01d0") (INSTANCE v_1.B1_i1) (DELAY (ABSOLUTE (IOPATH I ZN (1.151:1.151:1.151) (1.363:1.363:1.363) ) )) ) (CELL (CELLTYPE "pc5o06") (INSTANCE u1_2) (DELAY (ABS OLUTE (IOPATH I PAD (1.216:1.216:1.216) (1.249:1.249:1.249)) )) ) (CELL (CELLTYPE "pc5d01r") (INSTANCE u0_2) (DELAY (ABSOLUTE (IOPATH PAD CIN (.169:.169:.169) (.199:.199:.199)) )) )) __________________________________________________________________________ (DELAYFILE(DESIGN "MYDESIGN")(DATE "26 AUG 1996") (VENDOR "ASICS_INC") (PRO GRAM "SDF_GEN")(VERSION "3.0") (DIVIDER .) (VOLTAGE 3.6:3.3:3.0) (PROCESS "-3.0:0.0:3.0") (TEMPERATURE 0.0:25.0:115.0)(TIMESCALE )(CELL (CELLTYPE "A OI221") (INSTANCE X0) (DELAY (ABSOLUTE (IOPATH A1 Y (1.11:1.42:2.47) (1.3 9:1.78:3.19)) (IOPATH A2 Y (0.97:1.30:2.34) (1.53:1.94:3.50)) (IOPATH B1 Y (1.26:1.59:2.72) (1.52:2.01:3.79)) (IOPATH B2 Y (1.10:1.45:2.56) (1.66:2.18:4 .10)) (IOPATH C1 Y (0.79:1.04:1.91) (1.36:1.62:2.61)))))) __________________________________________________________________________ // comp_mux_rrr.vmodule comp_mux_rrr(a, b, clock, outp); input [2:0] a, b; outp ut [2:0] outp; input clock;reg [2:0] a_r, a_rr, b_r, b_rr, outp; reg sel_r;wire sel = ( a_r <= b_r ) ? 0 : 1; always @ (posedge clock) begin a_r <= a; b_r <= b; endalways @ (posedge clock) begin a_rr <= a_r; b_rr <= b_r; endalways @ (pos edge clock) outp <= sel_r ? b_rr : a_rr;always @ (posedge clock) sel_r <= sel;e ndmodule __________________________________________________________________________ entity Alarm is port(Clock, Key, Trip : in bit; Ring : out bit); end Alarm;a rchitecture RTL of Alarm is type States is (Armed, Off, Ringing); signal Stat e : States;begin process (Clock) begin if Clock = '1' and Clock'EVENT then case State is when Off => if Key = '1' then State <= Armed; end i f; when Armed => if Key = '0' then State <= Off; elsif Trip = '1' then State <= Ringing; end if; when Ringing => if Key = '0' then State <= Off; end if; end case; end if; end process; Ring <= '1' when State = Ringing else '0';end RTL; __________________________________________________________________________ library cells; use cells.all; // ...contains logic cell modelsarchitecture Gate s of Alarm iscomponent Inverter port(i : in BIT;z : out BIT) ; end component;co mponent NAnd2 port(a,b : in BIT;z : out BIT) ; end component;component NAnd3 po rt(a,b,c : in BIT;z : out BIT) ; end component;component DFF port(d,c : in BIT; q,qn : out BIT) ; end component;signal State, NextState : BIT_VECTOR(1 downto 0);signal s0, s1, s2, s3 : BIT;begin g2: Inverter port map ( i => State(0), z => s1 ); g3: NAnd2 port map ( a => s1, b => State(1), z => s2 ); g4: Inve rter port map ( i => s2, z => Ring ); g5: NAnd2 port map ( a => State(1), b = > Key, z => s0 ); g6: NAnd3 port map ( a => Trip, b => s1, c => Key, z => s3 ); g7: NAnd2 port map ( a => s0, b => s3, z => NextState(1) ); g8: Inverter port map ( i => Key, z => NextState(0) ); state_ff_b0: DFF port map ( d = > NextState(0), c => Clock, q => State(0), qn => open ); state_ff_b1: DFF por t map ( d => NextState(1), c => Clock, q => State(1), qn => open );end Gates ; __________________________________________________________________________ OB September 5, 1996 17:27.TRAN/OP 1ns 20ns.PROBE cl output Ground 10pF V IN input Ground PWL(0us 5V 10ns 5V 12ns 0V 20ns 0V) VGround 0 Ground DC 0V Vdd +5V 0 DC 5V m1 output input Ground Ground NMOS W=100u L=2u m2 output input +5V +5V PMOS W=200u L=2u .model nmos nmos level=2 vto=0.78 tox=400e-10 nsub=8.0e15 xj=-0.15e-6+ ld=0.20e-6 uo=650 ucrit=0.62e5 uexp=0.125 vmax=5.1e4 neff=4.0+ delta=1.4 rsh=37 cgso=2.95e-10 cgdo=2.95e-10 cj=195e-6 cj sw=500e-12+ mj=0.76 mjsw=0.30 pb=0.80.model pmos pmos level=2 vto=-0.8 tox=400e -10 nsub=6.0e15 xj=-0.05e-6+ ld=0.20e-6 uo=255 ucrit=0.86e5 uexp=0.29 vmax=3.0e 4 neff=2.65+ delta=1 rsh=125 cgso=2.65e-10 cgdo=2.65e-10 cj=250e-6 cjsw=350e-12 + mj=0.535 mjsw=0.34 pb=0.80.end __________________________________________________________________________ .MODEL NM1 NMOS LEVEL=4 + VFB=-0.7, LVFB=-4E-2, WVFB=5E-2+ PHI=0.84, LPHI=0, WP HI=0+ K1=0.78, LK1=-8E-4, WK1=-5E-2+ K2=2.7E-2, LK2=5E-2, WK2=-3E-2+ ETA=-2E-3, LETA=2E-02, WETA=-5E-3+ MUZ=600, DL=0.2, DW=0.5+ U0=0.33, LU0=0.1, WU0=-0.1+ U 1=3.3E-2, LU1=3E-2, WU1=-1E-2+ X2MZ=9.7, LX2MZ=-6, WX2MZ=7+ X2E=4.4E-4, LX2E=-3 E-3, WX2E=9E-4+ X3E=-5E-5, LX3E=-2E-3, WX3E=-1E-3+ X2U0=-1E-2, LX2U0=-1E-3, WX2 U0=5E-3+ X2U1=-1E-3, LX2U1=1E-3, WX2U1=-7E-4+ MUS=700, LMUS=-50, WMUS=7+ X2MS=- 6E-2, LX2MS=1, WX2MS=4+ X3MS=9, LX3MS=2, WX3MS=-6+ X3U1=9E-3, LX3U1=2E-4, WX3U1 =-5E-3+ TOX=1E-2, TEMP=25, VDD=5+ CGDO=3E-10, CGSO=3E-10, CGBO=4E-10+ XPART=1+ N0=1, LN0=0, WN0=0+ NB=0, LNB=0, WNB=0+ ND=0, LND=0, WND=0* n+ diffusion + RSH= 2.1, CJ=3.5E-4, CJSW=2.9E-10+ JS=1E-8, PB=0.8, PBSW=0.8+ MJ=0.44, MJSW=0.26, WD F=0*, DS=0 __________________________________________________________________________ .MODEL PM1 PMOS LEVEL=4 + VFB=-0.2, LVFB=4E-2, WVFB=-0.1+ PHI=0.83, LPHI=0, WPH I=0+ K1=0.35, LK1=-7E-02, WK1=0.2+ K2=-4.5E-2, LK2=9E-3, WK2=4E-2+ ETA=-1E-2, L ETA=2E-2, WETA=-4E-4+ MUZ=140, DL=0.2, DW=0.5+ U0=0.2, LU0=6E-2, WU0=-6E-2+ U1= 1E-2, LU1=1E-2, WU1=7E-4+ X2MZ=7, LX2MZ=-2, WX2MZ=1+ X2E= 5E-5, LX2E=-1E-3, WX2 E=-2E-4+ X3E=8E-4, LX3E=-2E-4, WX3E=-1E-3+ X2U0=9E-3, LX2U0=-2E-3, WX2U0=2E-3+ X2U1=6E-4, LX2U1=5E-4, WX2U1=3E-4+ MUS=150, LMUS=10, WMUS=4+ X2MS=6, LX2MS=-0.7 , WX2MS=2+ X3MS=-1E-2, LX3MS=2, WX3MS=1+ X3U1=-1E-3, LX3U1=-5E-4, WX3U1=1E-3+ T OX=1E-2, TEMP=25, VDD=5+ CGDO=2.4E-10, CGSO=2.4E-10, CGBO=3.8E-10+ XPART=1+ N0= 1, LN0=0, WN0=0+ NB=0, LNB=0, WNB=0+ ND=0, LND=0, WND=0* p+ diffusion + RSH=2, CJ=9.5E-4, CJSW=2.5E-10+ JS=1E-8, PB=0.85, PBSW=0.85+ MJ=0.44, MJSW=0.24, WDF=0 *, DS=0 __________________________________________________________________________