/* ATENÇÃO: ESTE É CABEÇALHO-COMPLETO para COMPONENTES-DE2.
   Recursos: chaves(SW), leds(LEDR e LEDG), lcd, áudio, vídeo, etc estão
   presentes aqui.
   Importante: Esse cabeçalho é necessário para seus PROJETOS funcionarem!!!!
   Lembre-se: é necessário também incluir PINAGENS nos seus projetos. \o/
*/

module DE2_TOP (

////////////////////////	Clock Input	 	////////////////////////
input			CLOCK_27,				//	27 MHz
input			CLOCK_50,				//	50 MHz
input			EXT_CLOCK,				//	External Clock
////////////////////////	Push Button		////////////////////////
input	[3:0]	KEY,					//	Pushbutton[3:0]
////////////////////////	DPDT Switch		////////////////////////
input	[17:0]	SW,						//	Toggle Switch[17:0]
////////////////////////	7-SEG Dispaly	////////////////////////
output logic	[6:0]	HEX0,					//	Seven Segment Digit 0
output logic	[6:0]	HEX1,					//	Seven Segment Digit 1
output logic	[6:0]	HEX2,					//	Seven Segment Digit 2
output logic	[6:0]	HEX3,					//	Seven Segment Digit 3
output logic	[6:0]	HEX4,					//	Seven Segment Digit 4
output logic	[6:0]	HEX5,					//	Seven Segment Digit 5
output logic	[6:0]	HEX6,					//	Seven Segment Digit 6
output logic	[6:0]	HEX7,					//	Seven Segment Digit 7
////////////////////////////	LED		////////////////////////////
output logic	[8:0]	LEDG,					//	LED Green[8:0]
output logic	[17:0]	LEDR,					//	LED Red[17:0]
////////////////////////////	UART	////////////////////////////
output logic			UART_TXD,				//	UART Transmitter
input			UART_RXD,				//	UART Receiver
////////////////////////////	IRDA	////////////////////////////
output logic			IRDA_TXD,				//	IRDA Transmitter
input			IRDA_RXD,				//	IRDA Receiver
///////////////////////		SDRAM Interface	////////////////////////
inout	[15:0]	DRAM_DQ,				//	SDRAM Data bus 16 Bits
output logic	[11:0]	DRAM_ADDR,				//	SDRAM Address bus 12 Bits
output logic			DRAM_LDQM,				//	SDRAM Low-byte Data Mask 
output logic			DRAM_UDQM,				//	SDRAM High-byte Data Mask
output logic			DRAM_WE_N,				//	SDRAM Write Enable
output logic			DRAM_CAS_N,				//	SDRAM Column Address Strobe
output logic			DRAM_RAS_N,				//	SDRAM Row Address Strobe
output logic			DRAM_CS_N,				//	SDRAM Chip Select
output logic			DRAM_BA_0,				//	SDRAM Bank Address 0
output logic			DRAM_BA_1,				//	SDRAM Bank Address 0
output logic			DRAM_CLK,				//	SDRAM Clock
output logic			DRAM_CKE,				//	SDRAM Clock Enable
////////////////////////	Flash Interface	////////////////////////
inout	[7:0]	FL_DQ,					//	FLASH Data bus 8 Bits
output logic	[21:0]	FL_ADDR,				//	FLASH Address bus 22 Bits
output logic			FL_WE_N,				//	FLASH Write Enable
output logic			FL_RST_N,				//	FLASH Reset
output logic			FL_OE_N,				//	FLASH output logic Enable
output logic			FL_CE_N,				//	FLASH Chip Enable
////////////////////////	SRAM Interface	////////////////////////
inout	[15:0]	SRAM_DQ,				//	SRAM Data bus 16 Bits
output logic	[17:0]	SRAM_ADDR,				//	SRAM Address bus 18 Bits
output logic			SRAM_UB_N,				//	SRAM High-byte Data Mask
output logic			SRAM_LB_N,				//	SRAM Low-byte Data Mask 
output logic			SRAM_WE_N,				//	SRAM Write Enable
output logic			SRAM_CE_N,				//	SRAM Chip Enable
output logic			SRAM_OE_N,				//	SRAM output logic Enable
////////////////////	ISP1362 Interface	////////////////////////
inout	[15:0]	OTG_DATA,				//	ISP1362 Data bus 16 Bits
output logic	[1:0]	OTG_ADDR,				//	ISP1362 Address 2 Bits
output logic			OTG_CS_N,				//	ISP1362 Chip Select
output logic			OTG_RD_N,				//	ISP1362 Write
output logic			OTG_WR_N,				//	ISP1362 Read
output logic			OTG_RST_N,				//	ISP1362 Reset
output logic			OTG_FSPEED,				//	USB Full Speed,	0 = Enable, Z = Disable
output logic			OTG_LSPEED,				//	USB Low Speed, 	0 = Enable, Z = Disable
input			OTG_INT0,				//	ISP1362 Interrupt 0
input			OTG_INT1,				//	ISP1362 Interrupt 1
input			OTG_DREQ0,				//	ISP1362 DMA Request 0
input			OTG_DREQ1,				//	ISP1362 DMA Request 1
output logic			OTG_DACK0_N,			//	ISP1362 DMA Acknowledge 0
output logic			OTG_DACK1_N,			//	ISP1362 DMA Acknowledge 1
////////////////////	LCD Module 16X2	////////////////////////////
inout	[7:0]	LCD_DATA,				//	LCD Data bus 8 bits
output logic			LCD_ON,					//	LCD Power ON/OFF
output logic			LCD_BLON,				//	LCD Back Light ON/OFF
output logic			LCD_RW,					//	LCD Read/Write Select, 0 = Write, 1 = Read
output logic			LCD_EN,					//	LCD Enable
output logic			LCD_RS,					//	LCD Command/Data Select, 0 = Command, 1 = Data
////////////////////	SD Card Interface	////////////////////////
inout			SD_DAT,					//	SD Card Data
inout			SD_DAT3,				//	SD Card Data 3
inout			SD_CMD,					//	SD Card Command Signal
output logic			SD_CLK,					//	SD Card Clock
////////////////////////	I2C		////////////////////////////////
inout			I2C_SDAT,				//	I2C Data
output logic			I2C_SCLK,				//	I2C Clock
////////////////////////	PS2		////////////////////////////////
input		 	PS2_DAT,				//	PS2 Data
input			PS2_CLK,				//	PS2 Clock
////////////////////	USB JTAG link	////////////////////////////
input  			TDI,					// CPLD -> FPGA (data in)
input  			TCK,					// CPLD -> FPGA (clk)
input  			TCS,					// CPLD -> FPGA (CS)
output logic 			TDO,					// FPGA -> CPLD (data out)
////////////////////////	VGA			////////////////////////////
output logic			VGA_CLK,   				//	VGA Clock
output logic			VGA_HS,					//	VGA H_SYNC
output logic			VGA_VS,					//	VGA V_SYNC
output logic			VGA_BLANK,				//	VGA BLANK
output logic			VGA_SYNC,				//	VGA SYNC
output logic	[9:0]	VGA_R,   				//	VGA Red[9:0]
output logic	[9:0]	VGA_G,	 				//	VGA Green[9:0]
output logic	[9:0]	VGA_B,   				//	VGA Blue[9:0]
////////////////	Ethernet Interface	////////////////////////////
inout	[15:0]	ENET_DATA,				//	DM9000A DATA bus 16Bits
output logic			ENET_CMD,				//	DM9000A Command/Data Select, 0 = Command, 1 = Data
output logic			ENET_CS_N,				//	DM9000A Chip Select
output logic			ENET_WR_N,				//	DM9000A Write
output logic			ENET_RD_N,				//	DM9000A Read
output logic			ENET_RST_N,				//	DM9000A Reset
input			ENET_INT,				//	DM9000A Interrupt
output logic			ENET_CLK,				//	DM9000A Clock 25 MHz
////////////////////	Audio CODEC		////////////////////////////
output logic/*inout*/	AUD_ADCLRCK,			//	Audio CODEC ADC LR Clock
input			AUD_ADCDAT,				//	Audio CODEC ADC Data
inout			AUD_DACLRCK,			//	Audio CODEC DAC LR Clock
output logic			AUD_DACDAT,				//	Audio CODEC DAC Data
inout			AUD_BCLK,				//	Audio CODEC Bit-Stream Clock
output logic			AUD_XCK,				//	Audio CODEC Chip Clock
////////////////////	TV Devoder		////////////////////////////
input	[7:0]	TD_DATA,    			//	TV Decoder Data bus 8 bits
input			TD_HS,					//	TV Decoder H_SYNC
input			TD_VS,					//	TV Decoder V_SYNC
output logic			TD_RESET,				//	TV Decoder Reset
input			TD_CLK,					//	TV Decoder Clock
////////////////////////	GPIO	////////////////////////////////
inout	[35:0]	GPIO_0,					//	GPIO Connection 0
inout	[35:0]	GPIO_1					//	GPIO Connection 1

);


always_comb begin
  	HEX0		=	7'h00;
  	HEX1		=	7'h00;
  	HEX2		=	7'h00;
  	HEX3		=	7'h00;
  	HEX4		=	7'h00;
  	HEX5		=	7'h00;
  	HEX6		=	7'h00;
  	HEX7		=	7'h00;
  	LEDG		=	9'h1FF;
  	LEDR		=	18'h3FFFF;
  	LCD_ON		=	1'b1;
  	LCD_BLON	=	1'b1;

//	All inout port turn to tri-state
  	DRAM_DQ		=	16'hzzzz;
  	FL_DQ		=	8'hzz;
  	SRAM_DQ		=	16'hzzzz;
  	OTG_DATA	=	16'hzzzz;
  	LCD_DATA	=	8'hzz;
  	SD_DAT		=	1'bz;
  	I2C_SDAT	=	1'bz;
  	ENET_DATA	=	16'hzzzz;
  	AUD_ADCLRCK	=	1'bz;
  	AUD_DACLRCK	=	1'bz;
  	AUD_BCLK	=	1'bz;
  	GPIO_0		=	36'hzzzzzzzzz;
  	GPIO_1		=	36'hzzzzzzzzz;
end

endmodule