// Filename: basics.sv (was uvm_basics_complete.sv)

//----------------------------------------------------------------------
//  Copyright (c) 2011 by Doulos Ltd.
//
//  Licensed under the Apache License, Version 2.0 (the "License");
//  you may not use this file except in compliance with the License.
//  You may obtain a copy of the License at
//
//  http://www.apache.org/licenses/LICENSE-2.0
//
//  Unless required by applicable law or agreed to in writing, software
//  distributed under the License is distributed on an "AS IS" BASIS,
//  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//  See the License for the specific language governing permissions and
//  limitations under the License.
//----------------------------------------------------------------------

// Source code example for Mentor Graphics Verification Academy UVM Basics Module
// Sessions 3-8

// Author: John Aynsley, Doulos
// Date:   10-Mar-2011

// modified by Elmar 11/11/12

// usage in Incisive 12.1:
// irun -uvm  -access +r +uvm_set_config_int="*",recording_detail,1 -coverage all -covoverwrite basic.sv +UVM_VERBOSITY=LOW
// simvision
// iccr -test test
//    report_detail *; exit

// usage in vcs G-2012.09 (for 64 bits use option -full64 or export VCS_TARGET_ARCH=amd64):
// vcs -sverilog basic.sv -ntb_opts uvm -debug_pp -R +plusarg_save +UVM_TR_RECORD +UVM_VERBOSITY=LOW
// dve -vpd vcdplus.vpd

// usage in Questa 10.1d:
// qverilog basic.sv -R -uvmcontrol=all +uvm_set_config_int="*",recording_detail,400 +UVM_VERBOSITY=LOW
// vsim -view vsim.wlf

// clean:
// rm -rf *.trn *.dsn INCA_libs cov_work *.log certe_dump.xml qverilog.log transcript vsim.wlf work uvm_basics_complete.log

`include "uvm_macros.svh"

interface dut_if();

  logic clock, reset;
  logic cmd;
  logic [7:0] data;

endinterface: dut_if


module dut(dut_if _if);

  import uvm_pkg::*;

  always @(posedge _if.clock)
  begin
  end
  
endmodule: dut


package my_seq_library;

  import uvm_pkg::*;

  class my_transaction extends uvm_sequence_item;
  
    rand bit cmd;
    rand int data;

    `uvm_object_utils_begin(my_transaction)
      `uvm_field_int(cmd, UVM_ALL_ON)
      `uvm_field_int(data, UVM_ALL_ON)
    `uvm_object_utils_end
  
    constraint c_data { data >= 0; data < 256; }
    
    function new (string name = "");
      super.new(name);
    endfunction: new
    
    function string convert2string;
      return $psprintf("cmd=%b, data=%0d", cmd, data);
    endfunction: convert2string

  endclass: my_transaction

  class command_sequence extends uvm_sequence #(my_transaction);
  
    `uvm_object_utils(command_sequence)
    
    function new (string name = "");
      super.new(name);
    endfunction: new

    task body;
      my_transaction tx;

      forever
      begin
        tx = my_transaction::type_id::create("tx");
        start_item(tx);
        assert( tx.randomize() );
        finish_item(tx);
      end

    endtask: body
   
  endclass: command_sequence
 
endpackage: my_seq_library


package my_pkg;

  import uvm_pkg::*;
  import my_seq_library::*;

  class my_driver extends uvm_driver #(my_transaction);
  
    `uvm_component_utils(my_driver)

    virtual dut_if dut_vi;

    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction: new
    
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      assert( uvm_config_db #(virtual dut_if)::get(this, "", "dut_vi", dut_vi) );
    endfunction : build_phase
   
    task run_phase(uvm_phase phase);
      forever
      begin
        my_transaction tx;
        
        seq_item_port.get_next_item(tx);
        @(posedge dut_vi.clock);

        // Wiggle pins of DUT
        dut_vi.cmd  = tx.cmd;
        dut_vi.data = tx.data;

        seq_item_port.item_done();
      end
    endtask: run_phase

  endclass: my_driver


  class my_monitor extends uvm_monitor;
  
    `uvm_component_utils(my_monitor)

    uvm_analysis_port #(my_transaction) aport;
    
    virtual dut_if dut_vi;

    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction: new
    
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      aport = new("aport", this);
      assert( uvm_config_db #(virtual dut_if)::get(this, "", "dut_vi", dut_vi) );
    endfunction : build_phase
   
    task run_phase(uvm_phase phase);
      forever
      begin
        my_transaction tx;
        tx = my_transaction::type_id::create("tx");
        tx.enable_recording("my_monitor");
        
        assert(begin_tr(tx, "my_monitor"));
        @(posedge dut_vi.clock);
        tx.cmd  = dut_vi.cmd;
        tx.data = dut_vi.data;
        this.end_tr(tx);
        
        aport.write(tx);
      end
    endtask: run_phase

  endclass: my_monitor

  typedef uvm_sequencer #(my_transaction) my_sequencer;

  class my_agent extends uvm_agent;

    `uvm_component_utils(my_agent)
    
    uvm_analysis_port #(my_transaction) aport;
    
    my_sequencer my_sequencer_h;
    my_driver    my_driver_h;
    my_monitor   my_monitor_h;
    
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction: new
    
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      aport = new("aport", this);
      my_sequencer_h = my_sequencer::type_id::create("my_sequencer_h", this);
      my_driver_h    = my_driver   ::type_id::create("my_driver_h"   , this);
      my_monitor_h   = my_monitor  ::type_id::create("my_monitor_h"  , this);
    endfunction: build_phase
    
    function void connect_phase(uvm_phase phase);
      my_driver_h.seq_item_port.connect( my_sequencer_h.seq_item_export );
      my_monitor_h.       aport.connect( aport );
    endfunction: connect_phase
    
  endclass: my_agent
  
  
  class my_subscriber extends uvm_subscriber #(my_transaction);
    `uvm_component_utils(my_subscriber)
   protected uvm_phase running_phase;
    
   my_transaction tx;
   covergroup cover_bus;
      coverpoint tx.cmd;
      coverpoint tx.data {
        bins d[4] = {[0:255]};
        option.at_least = 3;
      }
    endgroup: cover_bus
    
    function new(string name, uvm_component parent);
      super.new(name, parent);
      cover_bus = new;  
    endfunction: new

    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
    endfunction: build_phase
    
    task run_phase(uvm_phase phase);
      running_phase = phase;
      running_phase.raise_objection(this);
    endtask: run_phase

    function void write(my_transaction t);
      `uvm_info("ja", $psprintf("Subscriber received tx %s", t.convert2string()), UVM_NONE);
      tx= t;
      cover_bus.sample();
      `uvm_info("ja", $psprintf("Total coverage %d%%",$get_coverage()), UVM_NONE);
      if($get_coverage() > 99) running_phase.drop_objection(this);
    endfunction: write

  endclass: my_subscriber
  
  
  class my_env extends uvm_env;

    `uvm_component_utils(my_env)
    
    UVM_FILE file_h;
    my_agent      my_agent_h;
    my_subscriber my_subscriber_h;
    
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction: new
    
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      my_agent_h      = my_agent     ::type_id::create("my_agent_h", this);
      my_subscriber_h = my_subscriber::type_id::create("my_subscriber_h", this);
    endfunction: build_phase
    
    function void connect_phase(uvm_phase phase);
      my_agent_h.aport.connect( my_subscriber_h.analysis_export );
    endfunction: connect_phase
    
    function void start_of_simulation_phase(uvm_phase phase);
      file_h = $fopen("uvm_basics_complete.log", "w");
      uvm_top.set_report_default_file_hier(file_h);
      uvm_top.set_report_severity_action_hier(UVM_INFO, UVM_DISPLAY + UVM_LOG);
    endfunction: start_of_simulation_phase

  endclass: my_env
  
  
  class my_test extends uvm_test;
  
    `uvm_component_utils(my_test)
    
    my_env my_env_h;   
   
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction: new
    
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      my_env_h = my_env::type_id::create("my_env_h", this);
    endfunction: build_phase
    
    task run_phase(uvm_phase phase);
      command_sequence seq;
      seq = command_sequence::type_id::create("seq");
      seq.start( my_env_h.my_agent_h.my_sequencer_h );
    endtask: run_phase
    
  endclass: my_test
  
  
endpackage: my_pkg


module top;

  import uvm_pkg::*;
  import my_pkg::*;
  
  dut_if dut_if1 ();
  
  dut    dut1 ( ._if(dut_if1) );

  // Clock and reset generator
  initial begin
    dut_if1.clock = 0;
    forever #5 dut_if1.clock = ~dut_if1.clock;
  end

  initial  begin
    dut_if1.reset = 1;
    repeat(3) @(negedge dut_if1.clock);
    dut_if1.reset = 0;
  end

  initial
  begin: blk
    `ifdef INCA
       $recordvars();
    `endif
    `ifdef VCS
       $vcdpluson;
    `endif
    `ifdef QUESTA
       $wlfdumpvars();
    `endif
    uvm_config_db #(virtual dut_if)::set(null, "uvm_test_top.*", "dut_vi", dut_if1);
    run_test("my_test");
  end

endmodule: top