LADe.Projects History

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September 01, 2016, at 06:17 PM by fgassis - Describe RISC-V.BR project
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!! PLCM ''Chip''
!! RISC-V.BR ''Chip''

-> RISC-V.BR is a project developed since 2016 by [[ | Embedded Lab ]] as a part of the PEM initiative (Projects for Excellence in Microelectronics), which is the new home of the Brazil-IP team.

-> Objective: Develop a RISC-V based solution for Domestic Internet of Things (DIoT).

-> Description: An SoC will be developed integrating the [[#PLCM | PLCM IP-core]] and adding more functionality such as cryptography acceleration or a TrustZone implementation.

-> Application: SoC can be used as part of an intelligent system for monitoring energy consumption and home automation.

-> Project Phase: Planning

!! PLCM ''Chip'' [[#PLCM]]
July 04, 2012, at 05:35 PM by -
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!! SPVR ''Chip''

%center% %newwin% [[ | Attach:chip3333.png.jpg]]

-> Chip Speaker Verification System (spvR) or Voice Verification System, is a project developed since 2009 by the LAD through the federal program [[= Lad.Braziliplivre | Brazil-IP]].

-> Description: Chip can recognize the human voice.

-> Objective: To identify the voice of the person working as follows. You register on the system writes a code, usually a sentence, and the system will identify whether the user is who he is talking about actually being said. If the system does not recognize the voice, access to the site will be rejected automatically.

-> Results: The process of speech recognition takes place when the chip search parameters of the voice of a particular person realizes setting a model that each voice characteristic different from the others.

-> Application: Can be used in various environments such as homes, cars, computers, and other environments.

-> Project Phase: Completed

Related News:
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July 04, 2012, at 05:25 PM by -
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!! PLCM ''Chip''

-> Power Line Communication Modem IP Core (PLCM) is a project developed since 2012 by the LAD with a view to the federal program [[ | Brazil-IP]].

-> Objective: Develop an IP-core that implements the functionality of the physical layer of a PLC communication system (communication over mains) narrow-band.

-> Description: IP-core implement modulation and demodulation methods fully digital, analog interface such that a minimum is necessary for its use. Furthermore, it must deal with the effects of noise on the channel, implementing schemes for detection and correction of errors. As a modulation scheme, it is planned to use the S-FSK, as specified in IEC 61334-5-1.

-> Application: IP-Core can be used as part of an intelligent system for monitoring energy consumption and home automation. In this case, it could be triggered by a processor that implements higher layers of the communication system.

-> Project Phase: Completed

April 23, 2010, at 11:41 AM by Karina Silva -
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[[ Lad.mpeg4 | Project Page]]
[[ Lad.mpeg4 | MPEG-4]]
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[[ Lad.eTBc | Project Page ]]
[[ Lad.eTBc | eTBc ]]
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[[ Lad.VeriSC | Project Page ]]
[[ Lad.VeriSC | VeriSC ]]
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[[ Lad.VeriSC | Project Page ]]

[[ | << Back
[[ Lad.VeriSC | Project Page ]]
August 24, 2007, at 02:40 AM by -
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[[ | << Back ]]
August 24, 2007, at 02:28 AM by -
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!!!MPEG-4 ''Chip''
[[ Lad.mpeg4 | Project Page]]
%center%[[#blank | Attach:chip_board_shadow.png]]
!!!eTBc(''Easy Test Bench Creator'')
[[ Lad.eTBc | Project Page ]]
!!!VeriSC - Verification Functional Methodology
[[ Lad.VeriSC | Project Page ]]