Our document talks about DPI which is a light weight interface to C. You are probably aware that at present there is no standard which talks about SystemVerilog and SystemC interoperability. That is why you did not find any mention of SystemC in our documentation. There is a committee which is working on defining this interface. If you are interested in knowing more about this please let me know and I will send you some links. However, can you interoperate between SystemC and SV? the answer is yes. You have to be careful with data type mapping, threading, and synchronization between the two languages and simulators.
The SoC Verification KIT, at present, does not have any SystemC interface, ie: there are no reference models, or other functional models written in SystemC.